Digital Clock program By VHDL

OBJECTIVE:-    Digital Clock By VHDL 

Program :- 

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity digitalclk2 is
    Port ( clk : in std_logic;
           s,m,h : out integer := 0 );
end digitalclk2;

architecture Behavioral of digitalclk2 is

begin
Process(clk)
variable s1 : integer := -1 ;
Variable  m1,h1 : integer := 0 ;
begin
if(clk = '1') then
s1 := s1 +1 ;
   s <= s1  ;
   end if ;
   if(s1= 60)then
   s1:= 0 ;
   s <= s1;
   m1 := m1+1 ;
m   <= m1;
   end if ;
   if(m1= 60)then
   m1:=0 ;
   m <= m1;
   h1:= h1 + 1;
   h <= h1;
   end if ;
   if(h1= 24)then
   h1:= 0 ;
   m1:= 0 ;
   s1:= 0 ;
   end if ;
   end process;
end Behavioral;

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DESCRIPTION:-

·         A digital clock is a type of clock that displays the time digitally, i.e. in cyphers, as opposed to an analog clock, where the time is displayed by hands.

·         We use behavioral modeling style in this project . In the behavioral modeling we use if else statement .

·         We use integer counter for count the second,minut and hour .

·         Every 60 count we do the change or increment in the minut .

·        Syntax of if else statement :-

if <condition> then
statements
...
[
elsif <condition> then
statements
...
else
statements
...
]
end if;

·         here we takes three variables second , minute  and hour .

·         we  gives the condition that every 60 count variable takes a increment in minute variable and every 60 of minute variable ,hour variable take a increment .

·         when hour variable counter show 24 then every second ,minute and hour variable will be zero  .

COMPONENTS REQUIRED:-

                    i.            Xilinx project navigator (software)

                  ii.            Modelsim 5.4(software)

                iii.            FPGA board (hardware )

Application :-

·         In The Intelligent Digital Clock :- Intelligent Digital Clock with Ability to Communicate with PC has optional battery backup for 72 hours .

·         In Digital Clocks These clocks are designed to be used in industries or common waiting halls like Airports, Railway Stations, Hospitals etc.

·         Today digital clock are used in many electronics circuit where we want a specific task after a particular time .

Traffic light controller by VHDL with FPGA

Traffic light controller by VHDL by FPGA :- 

TRAFFIC  LIGHT  CONTROLLER   IN  VHDL:-

OBJECTIVE:-

                   This project is used for control the traffic at a circle. At the circle the traffic will be flow and stop by the three lights.

VHDL CODE :- 

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

entity trafica is
    Port ( clk : in  STD_LOGIC;
           p2 : out  STD_LOGIC_vector(11 downto 0) );
end trafica;


architecture functions of trafica is
begin

process(clk)
variable m:std_logic_vector(24 downto 0):=(others=>'0');
variable n : integer := 0 ;
variable p1 : std_logic_vector(11 downto 0);

begin
if(rising_edge(clk))then
if(m < "1011111010111100001000000")then
m:=m+1;
else
m:=(others=>'0');
n := n + 1;
end if;
end if;

if(n = 1 )then
p1(2 downto 0) := "001";
p1(5 downto 3):= "100";
p1(8 downto 6) := "100";
p1(11 downto 9) := "100";
end if ;

 if( n = 11 )then
p1(2 downto 0) := "010";
 end if ;

 if (n = 14)then
 p1(2 downto 0) := "100";
p1(5 downto 3) := "001";
 end if ;

if (n = 25)then
 p1(2 downto 0) := "100";
p1(5 downto 3) := "010";
 end if ;

 if (n = 29)then
 p1(2 downto 0) := "100";
p1(5 downto 3) := "100";
p1(8 downto 6) := "001";
 end if ;

 if (n = 40)then
 p1(2 downto 0):= "100";
p1(5 downto 3):= "100";
p1(8 downto 6) := "010";
 end if ;

 if(n = 44 )then
p1(2 downto 0) := "100";
p1(5 downto 3) := "100";
p1(8 downto 6) := "100";
p1(11 downto 9) := "001";
end if ;

IF(n = 55 )then
p1(2 downto 0) := "100";
p1(5 downto 3) := "100";
p1(8 downto 6) := "100";
p1(11 downto 9) := "010";
end if ;

if(n = 59 )then
 n  := 0;
end if ;

p2<= p1;

end process;
end functions;


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SAMPLE IMAGE:-

Features :-

·         It uses a counter so user can change the time for a particular way.

·         It uses a clock pulse at which every rising edge it gives the output.

·         In this project we take the three output while input is one .

DESCRIPTION:-

·         In this project we use behavioral modeling style by if else statement.

Syntax of if else statement

if <condition> then

statements
...

[
elsif <condition> then

statements
...
else

statements
...

]

End if;

·         We gives a clock pulse at a input so that it gives the output at a every rising edge of clock.

·         For the four way we makes a four counter .

·         At the output we takes the three output of std_logic_vector (3 downto 0) for the four ways.

·         Counter takes a increment in present value at a every rising edge of clock .

COMPONENTS REQUIRED:-

       I.            Xilinx Prject navigator(6.1)

    II.            Modelsim 5.4

 III.            Spartan 3e kit FPGA board

WORKS TO DO IN REQUIRED ORDER:-

                               I.            We installed the project navigator software in computer with include modelsim 5.4.

                            II.            We makes a integer counter for a particular time period .

                         III.            A integer counter counts the values in integer formate.

                         IV.            Now open a single way at a time instat while all others are close .

                            V.            Now we run this code at project navigator and improve the errors and after that check the RTL.

                         VI.            Now burn the code in FPGA kit .

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For B.Tech / M.tech Thesis and projects 

And Gate Program By VHDL

And Gate Program By VHDL :-


Program for AND GATE by use of VHDL:-

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---Designed by VLSI Engi Tech Pvt. Ltd.

Entity andgate is
    Port ( a,b : in std_logic;
           c : out std_logic);
end andgate;

architecture Behavioral of andgate is

begin

c <= a and b ;

end Behavioral;

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RTL View of AND GATE program by VHDL :-

AND Gate Program Description :-

1:- Firstly we will declare Library in which  all the definitions are installed for Packages .
2:- Std_logic_1164 is a package which contains 9 types of Values .
3:- Entity is a collection of Input and Output Ports .
4:- Architecture will define Basic Architecture module of an IC . There are two inputs a,b / one output c .
     And Operation is performing between a , b while output is coming in c .