And Gate Program By VHDL

And Gate Program By VHDL :-


Program for AND GATE by use of VHDL:-

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library IEEE;
use IEEE.STD_LOGIC_1164.ALL;
use IEEE.STD_LOGIC_ARITH.ALL;
use IEEE.STD_LOGIC_UNSIGNED.ALL;

---Designed by VLSI Engi Tech Pvt. Ltd.

Entity andgate is
    Port ( a,b : in std_logic;
           c : out std_logic);
end andgate;

architecture Behavioral of andgate is

begin

c <= a and b ;

end Behavioral;

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RTL View of AND GATE program by VHDL :-

AND Gate Program Description :-

1:- Firstly we will declare Library in which  all the definitions are installed for Packages .
2:- Std_logic_1164 is a package which contains 9 types of Values .
3:- Entity is a collection of Input and Output Ports .
4:- Architecture will define Basic Architecture module of an IC . There are two inputs a,b / one output c .
     And Operation is performing between a , b while output is coming in c .